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ltc 4233 1 4233f for more information www.linear.com/ltc4233 typical application features description 10a guaranteed soa hot swap controller the lt c ? 4233 is an integrated solution for hot swap ? applications that allows a board to be safely inserted and removed from a live backplane . the part integrates a hot swap controller , power mosfet and current sense resis - tor in a single package for small form factor applications . the mosfet safe operating area is production tested and guaranteed for the stresses in hot swap applications . the ltc4233 provides separate inrush current control and an 11% accurate 11.2 a current limit with output dependent foldback . the current limit threshold can be adjusted dynamically using the i set pin . additional features include a current monitor output that amplifies the sense resistor voltage for ground referenced current sensing and a mosfet temperature monitor output . thermal limit , overvoltage, undervoltage and power good monitoring are also provided . for a 20 a pin compatible version see ltc4234. 12v, 10a card resident application with auto-retry applications n allows safe board insertion into a live backplane n small footprint n 10m mosfet including r sense n safe operating area guaranteed at 41w, 30ms n wide operating voltage range: 2.9v to 15v n adjustable, 11% accurate current limit n current and temperature monitor outputs n overtemperature protection n adjustable current limit timer before fault n power good and fault outputs n adjustable inrush current control n 2.5% accurate undervoltage and overvoltage protection n available in 38-lead (5mm 9mm) qfn package n pin compatible with ltc4234 n high availability servers n solid state drives n industrial n network routers and switches l , lt , lt c , lt m , linear technology and the linear logo are registered trademarks and hot swap and powerpath are trademarks of linear technology corporation. all other trademarks are the property of their respective owners. power-up waveforms ltc4233 *tvs: diodes inc. smaj17a gnd v dd uv f lt ov sense C sensetimer intv cc out fb pg i mon i set gate 150k20k 107k * 5.23k 10k 1f 680f v out 12v10a 20k 4233 ta01a 10k adc + 12v 20ms/div contact bounce v in 10v/div i in 0.2a/div v out 10v/div pg 10v/div 4233 ta01b downloaded from: http:///
ltc 4233 2 4233f for more information www.linear.com/ltc4233 pin configuration absolute maximum ratings supply voltage (v dd ) ................................. C0.3 v to 28 v input voltages fb , ov , uv .............................................. C0.3 v to 12 v timer ................................................... C0.3 v to 3.5 v sense C , sense ..... v dd ? 10 v or C0.3 v to v dd + 0.3 v output voltages i set , i mon ................................................. C0.3 v to 3v pg , flt ................................................. C0.3 v to 35 v out ............................................ C0.3 v to v dd + 0.3 v intv cc .................................................. C0.3 v to 3.5 v gate ( note 3) ........................................ C0.3 v to 33 v operating ambient temperature range ltc 4234 c ................................................ 0 c to 70 c ltc 4234 i ............................................. C40 c to 85 c ltc 4234 h .......................................... C40 c to 125 c junction temperature ( note 4, 5) ......................... 150 c storage temperature range .................. C65 c to 150 c (notes 1, 2) top view 39 v dd 40 sense whh package 38-lead plastic qfn (5mm 9mm) uvov i mon timer intv cc v dd (dnc) gnd sense (dnc) outout out out out out out out 12 3 4 5 6 7 8 9 10 11 12 13 14 15 16 3837 36 35 34 33 32 31 30 29 28 27 26 25 24 23 outout out i set fb f lt pg sense C v dd (dnc) gate sense out out out out out out out out outout out 1718 19 20 21 22 t jmax = 150c, ja = 15c/w exposed pad (pins 39 and 40) are vdd and sense, ja = 15c/w soldered, otherwise ja = 50c/w order information lead free finish tape and reel part marking package description temperature range ltc4233cwhh#pbf ltc4233cwhh#trpbf 4233 38-lead (5mm 9mm) plastic qfn 0c to 70c ltc4233iwhh#pbf ltc4233iwhh#trpbf 4233 38-lead (5mm 9mm) plastic qfn C40c to 85c ltc4233hwhh#pbf ltc4233hwhh#trpbf 4233 38-lead (5mm 9mm) plastic qfn C40c to 125c consult ltc marketing for parts specified with wider operating temperature ranges. consult ltc marketing for information on nonstandard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ downloaded from: http:///
ltc 4233 3 4233f for more information www.linear.com/ltc4233 symbol parameter conditions min typ max units dc characteristicsv dd input supply range l 2.9 15 v i dd input supply current mosfet on, no load l 1.6 3 ma v dd(uvl) input supply undervoltage lockout v dd rising l 2.63 2.73 2.85 v i out out leakage current v out = v gate = 0v, v dd = 15v v out = v gate = 12v l l 1 0 2 300 4 a a dv gate /dt out turn-on ramp rate gate open l 0.15 0.3 0.6 v/ms r on mosfet + sense resistor on-resistance c-grade, i-grade h-grade l l 4.5 4.5 10 10 14.5 16.5 m m i lim(th) current limit threshold v fb = 1.35v, i set open v fb = 0v, i set open v fb = 1.35v, r set = 20k l l l 10 2.0 4.7 11.2 2.8 5.6 12.4 3.7 6.4 a a a soa mosfet safe operating area v ds = 13.5v, 3a folded back, 50w 2 s (note 6) v ds = 7.5v, 11a onset of foldback, 50w 2 s (note 7) 30 7 ms ms inputsi in ov, uv, fb input current v = 1.2v l 0 1 a i sense ? (in) sense ? input current v sense C = 12v l 4 10 a v th ov, uv, fb threshold voltage v pin rising l 1.205 1.235 1.265 v v ov(hyst) ov hysteresis l 10 20 30 mv v uv(hyst) uv hysteresis l 50 80 110 mv v uv( rth ) uv reset threshold voltage v uv falling l 0.55 0.62 0.7 v v fb(hyst) fb power good hysteresis l 10 20 30 mv r iset i set internal resistor l 19 20 21 k outputsv intvcc intv cc output voltage v dd = 5v,15v, i sink = 0ma, C10ma l 2.8 3.1 3.3 v ol pg, f lt pin output low voltage i sink = 2ma l 0.4 0.8 v i oh pg , f lt pin input leakage current v = 30v l 0 10 a v timer(h) timer high threshold v timer rising l 1.2 1.235 1.28 v v timer(l) timer low threshold v timer falling l 0.1 0.21 0.3 v i timer(up) timer pull up current v timer = 0v l C80 C100 C120 a i timer(dn) timer pull down current v timer = 1.2v l 1.4 2 2.6 a i timer(ratio) timer current ratio i timer(dn) /i timer(up) l 1.6 2 2.7 % a imon i mon current gain l 9 10 10.5 a/a bw imon i mon bandwidth 250 khz i off(imon) i mon offset current i out = 300ma l 0 9 a i gate(up) gate pull-up current gate drive on, v gate = v out = 12v l C18 C24 C29 a i gate(dn) gate pull-down current gate drive off, v gate = 18v, v out = 12v l 180 250 500 a i gate(fst) gate fast pull-down current fast turn off, v gate = 18v, v out = 12v 140 ma electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v dd = 12v unless otherwise noted. downloaded from: http:///
ltc 4233 4 4233f for more information www.linear.com/ltc4233 the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v dd = 12v unless otherwise noted. electrical characteristics note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all currents into pins are positive; all voltages are referenced to gnd unless otherwise specified. note 3: an internal clamp limits the gate pin to a maximum of 6.5v above out. driving this pin to voltages beyond the clamp may damage the device. note 4: this ic includes overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperature will exceed 150c when overtemperature protection is active. continuous operation above the specified maximum operating junction temperature may impair device reliability. note 5: t j is calculated from the ambient temperature, t a , and power dissipation, p d , according to the formula: t j = t a + (p d ? 15c/w) note 6: soa tested at room temperature, soa (i.e. p 2 t) is reduced at elevated temperatures according to the following formula: p 2 t(t j ) = 50 w 2 s ?? ?? ? 150 c ? t j 150 c ? 25 c ?? ? ?? ? 2 note 7: guaranteed by design and extrapolated from p 2 t limit of 50w 2 s. symbol parameter conditions min typ max units ac characteristicst phl(gate) input high (ov), input low (uv) to gate low propagation delay v gate < 17.8v falling l 8 20 s t phl(ilim) short circuit to gate low v fb = 0, step v dd ? sense ? to 50mv, v gate < 15v falling l 1 5 s t d(on) turn-on delay step v uv to 2v, v gate > 13v l 24 48 72 ms t d(fault) uv low to clear fault latch delay 1 s t d(cb) circuit breaker filter delay time (internal) v fb = 0, step v dd ? sense C to 50mv l 1.2 2 2.7 ms t d(cool-down) cool down delay (internal) l 600 900 1200 ms downloaded from: http:///
ltc 4233 5 4233f for more information www.linear.com/ltc4233 typical performance characteristics t a = 25c, v dd = 12v unless otherwise noted. i dd vs v dd intv cc load regulation uv low-high threshold vs temperature uv hysteresis vs temperature timer pull-up current vs temperature current limit delay (t phl(ilim) vs overdrive) current limit threshold foldback current limit adjustment (i out vs r set ) r iset resistor vs temperature v dd (v) 0 1.0 i dd (ma) 1.4 1.8 2.2 5 10 15 20 4233 g01 25 30 C40c 25c 125c i load (ma) 0 0 0.5 1.51.0 intv cc (v) 3.52.0 2.5 3.0 4233 g02 C14 C12 C10 C8 C6 C4 C2 v dd = 5v v dd = 3.3v temperature (c) C50 uv low-high threshold (v) 1.2401.236 1.232 1.228 1.224 C25 0 25 4233 g03 50 75 150 100 125 temperature (c) C50 timer pull-up current (a) C110C105 C100 C95C90 C25 0 25 4233 g05 50 75 150 100 125 output current (a) 0 current propagation delay (s) 1000 100 10 1 0.1 10 20 30 4233 g06 40 50 60 fb voltage (v) 0 current limit value (a) 1210 42 86 0 0.2 4233 g07 0.4 0.6 1.2 0.8 1 >30ms soa guaranteed r set ( ) 1k current limit value (a) 1210 42 86 0 10k 4233 g08 100k 1m 10m temperature (c) C50 i set resistor (k) 2221 20 19 18 C25 0 25 4233 g09 50 75 150 100 125 temperature (c) C50 uv hysteresis (v) 0.100.08 0.06 0.04 C25 0 25 4233 g04 50 75 150 100 125 downloaded from: http:///
ltc 4233 6 4233f for more information www.linear.com/ltc4233 typical performance characteristics t a = 25c, v dd = 12v unless otherwise noted. r on vs temperature guaranteed mosfet soa curve i mon vs temperature gate drive vs gate pull-up current pg, f lt output low vs i sink gate pull-up current vs temperature gate drive vs v dd v iset vs temperature temperature (c) C50 r on (m) 1612 84 0 C25 0 25 4233 g10 50 75 150 100 125 v dd = 3.3v to 12v v ds (v) 0.1 i d (a) 100 10 1 0.1 1 10 4233 g12 100 >30ms soa guaranteed dc t a = 25c single pulse 3ms 30ms current (ma) 0 pg, flt v ol (v) 1412 10 84 2 60 2 4 6 4233 g12 8 10 12 temperature (c) C50 i mon (a) 105100 9585 9080 C25 0 25 4233 g13 50 75 150 100 125 v dd = 3.3v, 12v i load = 10a temperature (c) C50 i gate pull-up (a) C25.0C24.5 C24.0 C23.5 C23.0 C25 0 25 4233 g14 50 75 150 100 125 i gate (a) 0 0 ?v gate (v gate ? v out ) (v) 76 5 4 3 2 1 ?5 ?10 ?15 ?20 4233 g15 ?25 ?30 v dd = 12v v dd = 3.3v v dd (v) 0 6.26.0 5.8 5.6 5.4 5.2 5 10 15 4233 g16 20 25 30 ?v gate (v gate ? v out ) (v) temperature (c) C50 0.90.8 0.7 0.6 0.5 0.3 0.4 C25 0 25 4233 g18 50 75 150 100 125 v iset (v) junction temperature (c) 25 normalized p 2 t 1.00.4 0.2 0.80.6 0 50 4233 g11 75 150 100 125 soa constant vs junction temperature downloaded from: http:///
ltc 4233 7 4233f for more information www.linear.com/ltc4233 pin functions dnc: do not connect. leave open. fb: foldback and power good input. connect this pin to an external resistive divider from out . if the voltage falls below 0.6v, the current limit is reduced using a foldback profile ( see the typical performance characteristics sec - tion). if the voltage falls below 1.21v, the pg pin will pull low to indicate the power is bad f lt : overcurrent fault indicator . open-drain output pulls low when an overcurrent fault has occurred and the circuit breaker trips . for overcurrent auto-retry tie to uv pin (see applications information section for details). gate: gate drive for internal n-channel mosfet . an internal 24 a current source charges the gate of the n-channel mosfet . at start-up the gate pin ramps up at a 0.35 v/ ms rate determined by internal circuitry . during an undervoltage or overvoltage condition a 250 a pull-down current turns the mosfet off . during a short circuit or undervoltage lockout condition , a 140 ma pull-down cur - rent source between gate and out is activated. gnd: device ground. i mon : current monitor output . the current in the internal mosfet switch is divided by 100,000 and sourced from this pin . placing a 20 k resistor on this pin allows a 0 to 2v voltage swing when current ranges from 0a to 10a. intv cc : internal 3.1 v supply decoupling output . this pin must have a 1 f or larger bypass capacitor . overloading this pin can disrupt internal operation. i set : current limit adjustment pin . for 11.2 a current limit value open this pin . this pin is driven by a 20 k resistor in series with a voltage source . the pin voltage is used to generate the current limit threshold . the internal 20k resistor (r iset ) and an external resistor (r set ) between i set and ground create an attenuator that lowers the current limit value . due to circuit tolerance r set should not be less than 2k. in order to match the temperature variation of the sense resistor , the voltage on this pin is made proportional to temperature of the mosfet switch . out: output of internal mosfet switch . connect this pin directly to the load. ov: overvoltage comparator input . connect this pin to an external resistive divider from v dd . if the voltage at this pin rises above 1.235v, an overvoltage is detected and the switch turns off. tie to gnd if unused. pg: power good indicator . open drain output pulls low when the fb pin drops below 1.21 v indicating the power is bad. if the voltage at fb rises above 1.235 v and the gate to out voltage exceeds 4.2v, the open-drain pull-down releases the pg pin to go high.sense: current sense node and mosfet drain . one exposed pad on the uh package is connected to sense and should be soldered to an electrically isolated printed circuit board trace to properly transfer the heat out of the package. connect the sense pin 31 to the sense C pin 34. sense C : current limit and current monitor amplifier input. the current limit circuit controls the gate pin to limit the voltage between the v dd and sense C pins to 15mv (11.2a) or less depending on the voltage at the fb pin. this pin must be connected to sense pin on the right side (connect pin 34 to pin 31).timer: current limit timer input . connect a capacitor between this pin and ground to set a 12 ms / f duration for current limit before the switch is turned off . if the uv pin is toggled low while the mosfet switch is off , the switch will turn on again following cool-down time of 4.14s/ f duration . tie this pin to intv cc for a fixed 2ms overcurrent delay and 900ms cool-down time. uv: undervoltage comparator input . tie high to intv cc if unused . connect this pin to an external resistive divider from v dd . if the uv pin voltage falls below 1.15v, an un - dervoltage is detected and the switch turns off . pulling this pin below 0.62 v resets the overcurrent fault and allows the switch to turn back on ( see application information section for details ). if overcurrent auto-retry is desired then tie this pin to the flt pin. v dd : supply voltage and current sense input . this ex - posed pad must be soldered to input power . v dd has an undervoltage lockout threshold of 2.73v. downloaded from: http:///
ltc 4233 8 4233f for more information www.linear.com/ltc4233 functional block diagram 4233 bd v dd (exposed pad) uv out fb pg gnd i mon intv cc intv cc 100a timer f lt + C i set r iset 20k gate sense (exposed pad) sense C x1 clamp 0.6v positive temperature coefficient reference 8.6m mosfet 1.4m sense resistor charge pump and gate driver f = 2mhz 3.1v gen logic inrush cs cm 0.35v/ms 6.1v foldback 0.6v2.65v 1.235v +C + C pg 1.235v C + uv 0.21v C + tm1 1.235v C + tm2 0.62v C + rst v dd v dd 2.73v + C uvlo1 ov 1.235v C + ov 2a C + uvlo2 downloaded from: http:///
ltc 4233 9 4233f for more information www.linear.com/ltc4233 operation the functional block diagram displays the main circuits of the device . the ltc4233 is designed to turn a board s supply voltage on and off in a controlled manner allowing the board to be safely inserted and removed from a live backplane. the ltc4233 includes a 8.6m mosfet and a 1.4m current sense resistor . during normal opera - tion, the charge pump and gate driver turn on the pass mosfet s gate to provide power to the load . the inrush current control is accomplished by the inrush circuit . this circuit limits the gate ramp rate to 0.35v/ ms and hence controls the voltage ramp rate of the output capacitor.the current sense (cs) amplifier monitors the load current using the voltage sensed across the current sense resistor . the cs amplifier limits the current in the load by reduc - ing the gate-to-out voltage in an active control loop . it is simple to adjust the current limit threshold using the current limit adjustment (i set ) pin . this allows a different threshold during other times such as startup . note there must be a connection between sense to sense ? (pin 34 to pin 31) in order to monitor current. a short circuit on the output to ground causes significant power dissipation during active current limiting . to limit this power , the foldback amplifier reduces the current limit value from 11.2 a to 2.8 a in a linear manner as the fb pin drops below 0.6v ( see the typical performance characteristics). if an overcurrent condition persists , the timer pin ramps up with a 100 a current source until the pin voltage exceeds 1.235v ( comparator tm 2). this indicates to the logic that it is time to turn off the pass mosfet to prevent overheating. at this point the timer pin ramps down us - ing the 2 a current source until the voltage drops below 0.21v ( comparator tm 1) which completes one timer cycle . after eight timer pin cycles ( ramping to 1.235 v and then below 0.21v) the logic starts the internal 48 ms timer . at this point , the pass transistor has cooled and it is safe to turn it on again . it is suitable in many applications to use an internal 2 ms overcurrent timer with a 900 ms cool down period . tying the timer pin to intv cc sets this default timing . latchoff is the normal operating condition following overcurrent turnoff . retry is initiated by pulling the uv pin low for a minimum of 1 s then high . auto-retry is implemented by tying the f lt to the uv pin. the output voltage is monitored using the fb pin and the pg comparator to determine if the power is available for the load . the power good condition is signaled by the pg pin using an open-drain pull-down transistor. the functional block diagram shows the monitoring blocks of the ltc4233. the two comparators on the left side include the uv and ov comparators . these comparators are used to determine if the external conditions are valid prior to turning on the mosfet . but first the undervolt - age lockout circuits uvlo 1 and uvlo 2 must validate the input supply and the internally generated 3.1 v supply (intv cc ) and generate the power up initialization to the logic circuits . if the external conditions remain valid for 48ms the mosfet is allowed to turn on.other monitoring features include mosfet current and temperature monitoring . the current monitor ( cm ) outputs a current proportional to the sense resistor current . this current can drive an external resistor or other circuits for monitoring purposes . a voltage proportional to the mos - fet temperature is output to the i set pin . the mosfet is protected by a thermal shutdown circuit. downloaded from: http:///
ltc 4233 10 4233f for more information www.linear.com/ltc4233 the typical ltc4233 application is in a high availability system that uses a positive voltage supply to distribute power to individual cards . the complete application circuit is shown in figure 1. external component selection is discussed in detail in the following sections. turn-on sequence several conditions must be present before the internal pass mosfet can be turned on . first the supply v dd must exceed its undervoltage lockout level . next the internally generated supply intv cc must cross its 2.65 v undervolt - age threshold . this generates a 25 s power-on-reset pulse which clears the fault register and initializes internal latches . after the power-on-reset pulse , the uv and ov pins must indicate that the input voltage is within the acceptable range. all of these conditions must be satisfied for a du - ration of 48 ms to ensure that any contact bounce during the insertion has ended. the mosfet is turned on by charging up the gate with a charge pump generated 24 a current source whose value is adjusted by shunting a portion of the pull-up current to ground. the charging current is controlled by the inrush circuit that maintains a constant slope of gate voltage applications information versus time (figure 2). the voltage at the gate pin rises with a slope of 0.35[v/ms] and the supply inrush current is set at: i inrush = c l ? 0.35[v/ms] this gate slope is designed to charge up a 1000 f capaci - tor to 12 v in 34ms, with an inrush current of 350ma. this allows the inrush current to stay under the folded back current limit threshold (2.8 a) for capacitors less than 5 mf . included in the typical performance characteristics section is a graph of the safe operating area for the mosfet . it is evident from this graph that the power dissipation at 12v, 350ma for 34ms is in the safe region. figure 2. supply turn-on ltc4233 gnd v dd uv f lt ov sense C sensetimer intv cc out fb gate pg i set i mon r5150k r6 20k r gate 100k c gate 0.1f r1226k r2 20k r3140k z1* *tvs z1: diodes inc. smaj17a r420k c t 0.1f c l 330f v out 12v5a r mon 20k r set 20k 4233 f01 r710k adc + c1 1f 12v c comp 3.3nf uv = 9.88vov = 15.2v pg = 10.5v t1 t2 slope = 0.35[v/ms] gate out v dd + 6.15v v dd 4233 f02 figure 1. 5a, 12v card resident application downloaded from: http:///
ltc 4233 11 4233f for more information www.linear.com/ltc4233 applications information adding a capacitor and a 100 k series resistor from gate to ground will lower the inrush current below the default value set by the inrush circuit . the 3.3 nf capacitor , c comp , is necessary to compensate the current limit regulation loop when the r gate and c gate network is on the gate pin . the gate is charged with a 24 a current source (when inrush circuit is not driving the gate ). the voltage at the gate pin rises with a slope equal to 24a/c gate and the supply inrush current is set at: i inrush = c l c gate ? 24a when the gate voltage reaches the mosfet threshold voltage, the switch begins to turn on and the out volt - age follows the gate voltage as it increases . once out reaches v dd , the gate will ramp up until clamped by the 6.1v zener between gate and out. as the out voltage rises , so will the fb pin which is moni - toring it . once the fb pin crosses its 1.235 v threshold and the gate to out voltage exceeds 4.2v, the pg pin will cease to pull low and indicate that the power is good . parasitic mosfet oscillationwhen the n-channel mosfet ramps up the output during power-up it operates as a source follower . the source fol - lower configuration may self-oscillate in the range of 25khz to 300 khz when the load capacitance is less than 10f, especially if the wiring inductance from the supply to v dd pin is greater than 3h. the possibility of oscillations will increase as the load current ( during power-up ) increases . there are two ways to prevent this type of oscillation . the simplest way is to avoid load capacitances below 10f. for wiring inductances larger than 20h, the minimum load capacitance may extend to 100f. a second choice is to connect an external gate capacitor c p > 1.5 nf as shown in figure 3. turn-off sequence the switch can be turned off by a variety of conditions . a normal turn-off is initiated by the uv pin going below its 1.235 v threshold . additionally , several fault conditions will turn off the switch . these include an input overvolt - age ( ov pin ), overcurrent circuit breaker ( sense pin ) or overtemperature. normally the switch is turned off with a 250 a current pulling down the gate pin to ground . with the switch turned off , the out voltage drops which pulls the fb pin below its threshold . the pg then pulls low to indicate output power is no longer good.if v dd drops below 2.65 v for greater than 5 s or intv cc drops below 2.5 v for greater than 1s, a fast shutdown of the switch is initiated . the gate is pulled down with a 140ma current to the out pin.overcurrent fault the ltc4233 features an adjustable current limit with foldback that protects against short-circuits and exces - sive load current . to protect against excessive power dissipation in the switch during active current limit , the available current is reduced as a function of the output voltage sensed by the fb pin . a graph in the typical per - formance characteristics curves shows the current limit threshold foldback. figure 3. compensation for small c load 4233 f03 ltc4233 optional rc to lower inrush current gate c p 2.2nf downloaded from: http:///
ltc 4233 12 4233f for more information www.linear.com/ltc4233 applications information figure 4. short-circuit waveform an overcurrent fault occurs when the current limit circuitry has been engaged for longer than the timeout delay set by the timer . current limiting begins when the mosfet current reaches 2.8 a to 11.2a ( depending on the foldback ). the gate pin is then brought down with a 140 ma gate- to-out current . the voltage on the gate is regulated in order to limit the current to 11.2a. at this point , a circuit breaker time delay starts by charging the external timing capacitor with a 100 a pull-up current from the timer pin. if the timer pin reaches its 1.235 v threshold , the internal switch turns off ( with a 250 a current from gate to ground ). included in the typical performance characteristics curves is a graph of the safe operating area for the mosfet . from this graph one can determine the mosfet s maximum time in current limit for a given output power. tying the timer pin to intv cc will force the part to use the internally generated ( circuit breaker ) delay of 2ms. in either case the flt pin is pulled low to indicate an overcurrent fault has turned off the pass mosfet . for a given circuit breaker time delay , the equation for setting the timing capacitors value is as follows: c t = t cb ? 0.083[f/ms] after the switch is turned off , the timer pin begins dis - charging the timing capacitor with a 2 a pull-down cur - rent. when the timer pin reaches its 0.21 v threshold , it completes one timer cycle . after eight timer pin cycles ( ramping to 1.235 v and then below 0.21v) plus the 48ms debounce time the switch is allowed to turn on again if the overcurrent fault latch has been cleared . bringing the uv pin below 0.6 v for a minimum of 1 s and then high will clear the fault latch . if the timer pin is tied to intv cc then the switch is allowed to turn on again ( after an internal 900 ms cool down time plus the 48 ms debounce time ), if the overcurrent fault latch is cleared. tying the f lt pin to the uv pin allows the part to self-clear the fault and turn the mosfet on as soon as timer pin has ramped below 0.21 v for the eighth time followed by the 48 ms debounce time . in this auto-retry mode the ltc4233 repeatedly tries to turn on after an overcurrent at a period determined by the capacitor on the timer pin . the auto retry mode also functions when the timer pin is tied to intv cc . the waveform in figure 4 shows how the output latches off following a short circuit . the current in the mosfet is 2.8a as the timer ramps up. 1ms/div v out 10v/div i out 2a/div ?v gate 10v/div timer 2v/div 4233 f04 current limit adjustment the default value of the active current limit is 11.2a. the current limit threshold can be adjusted lower by placing a resistor between the i set pin and ground . as shown in the functional block diagram the voltage at the i set pin ( via the clamp circuit ) sets the cs amplifier s built-in offset voltage. this offset voltage directly determines the active current limit value . with the i set pin open , the voltage at the i set pin is determined by a positive temperature coefficient reference . this voltage is set to 0.618 v which corresponds to a 11.2 a current limit at room temperature . downloaded from: http:///
ltc 4233 13 4233f for more information www.linear.com/ltc4233 applications information an external resistor r set placed between the i set pin and ground forms a resistive divider with the internal 20 k r iset sourcing resistor . the divider acts to lower the voltage at the i set pin and therefore lower the current limit threshold . the overall current limit threshold precision is reduced to 15% when using a 20k resistor to halve the threshold. using a switch ( connected to ground ) in series with r set allows the active current limit to change only when the switch is closed . this feature can be used to program a reduced running current while the maximum available current limit is used at startup. monitor mosfet temperature the voltage at the i set pin increases linearly with increas - ing temperature . the temperature profile of the i set pin is shown in the typical performance characteristics section . using a comparator or adc to measure the i set voltage provides an accurate indication of the mosfet temperature . the i set voltage follows the formula: v iset = r set r set + r iset ? t + 273 c ( ) ? 2.093 mv/c [ ] the mosfet temperature is calculated using r iset of 20k. t = r set + 20k ( ) ? v iset r set ? 2.093[mv/c] ? 273 c when r set is not present, t becomes: t = v iset 2.093[mv/c] ? 273 c there is an overtemperature circuit in the ltc4233 that monitors an internal voltage similar to the i set pin voltage . when the die temperature exceeds 155 c the circuit turns off the mosfet until the temperature drops to 135c. monitor mosfet currentthe current in the mosfet passes through an internal 1.4m sense resistor . the voltage on the sense resistor is converted to a current that is sourced out of the i mon pin . the gain of i sense amplifier is 10a/ a referenced from the mosfet current . this output current can be converted to a voltage using an external resistor to drive a comparator or adc . the voltage compliance for the i mon pin is from 0v to intv cc ? 0.7v. a microcontroller with a built-in comparator can build a simple integrating single-slope adc by resetting a capaci - tor that is charged with this current . when the capacitor voltage trips the comparator and the capacitor is reset , a timer is started . the time between resets will indicate the mosfet current.monitor ov and uv faults protecting the load from an overvoltage condition is the main function of the ov pin . in figure 1 an external resis - tive divider ( driving the ov pin ) connects to a comparator to turn off the mosfet when the v dd voltage exceeds 15.2v. if the v dd pin subsequently falls back below 14.9v, the switch will be allowed to turn on immediately . in the ltc4233 the ov pin threshold is 1.235 v when rising , and 1.215v when falling out of overvoltage. the uv pin functions as an undervoltage protection pin or as an on pin . in the figure 1 application the mosfet turns off when v dd falls below 9.23 v. if the v dd pin subsequently rises above 9.88 v for 48ms, the switch will be allowed to turn on again . the ltc4233 uv turn-on / off threshold are 1.235v (rising) and 1.155v (falling). in the case of an undervoltage or overvoltage the mosfet turns off and there is indication on the pg status pin . when the overvoltage is removed , the mosfet s gate ramps up immediately at the rate determined by the inrush circuit . downloaded from: http:///
ltc 4233 14 4233f for more information www.linear.com/ltc4233 applications information the inrush current is defined by the current required to charge the output capacitor using the fixed 0.35 v/ ms gate charge up rate. the inrush current is defined as: i inrush = c l ? 0.35[v/ms] = 680f ? 0.35[v/ms] = 240ma as mentioned previously the charge-up time is the output voltage (12v) divided by the output rate of 0.35v/ms resulting in 34ms. the peak power dissipation of 12v at 240ma (or 2.9w) must not exceed the soa of the pass mosfet for 34ms ( see mosfet soa graph in the typical performance characteristics section ). on the soa graph the 30 ms line crosses the 10 v v ds vertical line at 4a. this verifies that the 40 w for 30 ms is safe at room temperature. each single point on the 3 ms and 30 ms lines represent a power ( voltage times current ) and time that follow a constant p 2 t relationship of 50w 2 s. if the mosfet junction temperature is elevated then the p 2 t constant must be derated . at t j = 60 the new constant becomes : p 2 t (t j = 60 c) = 50 w 2 s ?? ?? ? 150 c ? 60 c 150 c ? 25 c ? ? ? ? ? ? 2 = 26 w 2 s ?? ?? power good indicationin addition to setting the foldback current limit threshold , the fb pin is used to determine a power good condition . the figure 1 application uses an external resistive divider on the out pin to drive the fb pin . on the ltc4233 the pg comparator drives high when the fb pin rises above 1.235v and low when it falls below 1.215v. once the pg comparator is high the gate pin voltage is monitored with respect to the out pin . once the gate minus out voltage exceeds 4.2 v the pg pin goes high . this indicates to the system that it is safe to load the out pin while the mosfet is completely turned on . the pg pin goes low when the gate is commanded off (using the uv , ov or sense C pins ) or when the pg comparator drives low.design example consider the following design example ( figure 5): t a = 60c, v in = 12v, i max = 10a. i inrush = 240ma, c l = 680f, v uvon = 9.88v, v ovoff = 15.2v, v pgthreshold = 10.5v. a current limit fault triggers an automatic restart of the power up sequence. figure 5. 10a, 12v card resident application ltc4233 gnd v dd uv f lt ov sense C sensetimer intv cc out fb pg r5150k r6 20k r3140k r420k *tvs z1: diodes inc. smaj17a r1226k r220k c1 1f c l 680f v out 12v10a r mon 20k 4233 f05 r710k adc + 12v z1* uv = 9.88vov = 15.2v pg = 10.5v i set i mon gate downloaded from: http:///
ltc 4233 15 4233f for more information www.linear.com/ltc4233 applications information the maximum power for 34 ms can be calculated from the derated constant: p max = p 2 t(t j = 60 c) t = 26 w 2 s ?? ?? 34ms = 28w therefore, the power dissipation at charge-up is within the mosfet soa. next the power dissipated in the mosfet during overcur - rent must be limited . the active current limit uses a timer to prevent excessive energy dissipation in the mosfet . the worst-case power dissipation occurs when the volt - age versus current profile of the foldback current limit is at the maximum . this occurs when the current is 12.4a and the voltage is half of v in or 6v. see the current limit threshold foldback in the typical performance charac - teristics section to view this profile . in order to survive 74w, the mosfet soa dictates a maximum current limit timeout. if the mosfet operating temperature is elevated prior to current limit the soa constant must be derated according to the formula: p 2 t(t j ) = p 2 t(25 c) ? 150 c ? t j 150 c ? 25 c ? ? ? ? ? ? 2 t j is calculated from the ambient temperature , package thermal impedance ( ja ) and the i 2 r heating. t j = ( ja ? i 2 ? r on ) + t a = 15c/w ? (10a) 2 ? 14.5 m + 60c = 82?c using the soa derating formula: p 2 t(t j = 82 c) = 50 w 2 s ?? ?? ? 150 c ? 82 c 150 c ? 25 c ?? ? ?? ? 2 = 15 w 2 s ? ? ? ? so the soa constant is derated to 15w 2 s. the maximum current limit timeout is calculated from the revised constant and the 74w dissipated in current limit. t max = p 2 t t j = 82 c ( ) p 2 = 15 w 2 s ?? ?? 74w ( ) 2 = 2.7ms invoke the internal 2 ms timer by tying the timer pin to intv cc . to configure the ltc4233 for auto-retry after overcurrent fault , connect the f lt to the uv pin . after the 2 ms timeout the f lt pin pulls down on the uv pin restart the power-up sequence. the values for overvoltage , undervoltage and power good thresholds using the resistive dividers on the uv , ov and fb pins match the requirements of turn-on at 9.88 v and turn-off at 15.2v. the final schematic in figure 5 results in very few external components. the pull-up resistor , r 7, connects to the pg pin while the 20k (r mon ) converts the i mon current to a voltage at a ratio: v imon = 10[a/a] ? 20k ? i out = 0.2[v/a] ? i out in addition there is a 1 f bypass (c1) on the intv cc pin and note the connection between sense to sense ? (pin 34 to pin 31). downloaded from: http:///
ltc 4233 16 4233f for more information www.linear.com/ltc4233 applications information figure 6. recommended layout 4233 f06 out gnd c1 v dd v dd sense layout considerationsin hot swap applications where load currents can be 10a, narrow pcb tracks exhibit more resistance than wider tracks and operate at elevated temperatures . the minimum trace width requirement for 1 oz copper foil is 0.02" per amp to make sure the trace stays at a reasonable temperature . using 0.03" per amp or wider is recommended . note that 1 oz copper exhibits a sheet resistance of about 0.5m/ square. small resistances add up quickly in high current applications.the input supply should be tied to the v dd exposed pad through a pcb trace that enters between pin 1 and pin 38. the v dd pad connects to the sense resistor and mosfet . globally, there are three dnc pins that are unconnected and left open (pins 6, 8, 33). connect the sense C pin (pin 34) to the sense pin (pin 31). figure 6 shows a recom - mended layout for the ltc4233.during normal operation the power dissipated in the mosfet could be as high as 1.5w. to remove this heat , solder the sense exposed pad to a copper trace that contains vias underneath the pad . the out pins also conduct substantial heat from the mosfet . connect all the out pins to a plane of 1 oz copper . since the trace that connects out pins must accommodate high current , this area of copper is usually present . it is also important to put c 1, the bypass capacitor for the intv cc pin as close as possible between intv cc and gnd. downloaded from: http:///
ltc 4233 17 4233f for more information www.linear.com/ltc4233 thermal considerations the ltc4233 junction to board temperature rise in still air when the load current is 5a, 7.5 a and 10 a is shown in curves of figures 7 and 8. the junction temperature was measured at the package and the board temperature was measured at the board edge . this temperature rise falls as the board area is increases from 6.45 cm 2 to 103 cm 2 . two different sense pad areas are shown as separate figures . this thermal test board uses 2 oz copper on the top layer divided equally between v dd and out traces similar to figure 6. the second layer is 1 oz copper connected to the vias to the sense pad on the top layer . two versions of the second layer are considered . one uses a minimum applications information ?t jb (c) 0 a b (cm 2 ) 120 6040 100 8020 0 5 10 15 4233 f07 20 25 35 30 5a 7.5a 10a small sense pad (2nd layer) ?t jb (c) 0 a b (cm 2 ) 120 6040 100 8020 0 5 10 15 20 25 35 30 5a 7.5a 10a 4233 f08 large sense pad (2nd layer) figure 7. temperature rise for small sense pad figure 8. temperature rise for large sense pad sized sense pad that only covers the vias for the top layer while the remainder of the second layer is empty ( see figure 7). the other version fills the second layer with sense connected copper ( see figure 8). the third layer is 1 oz copper tied to ground while the bottom layer is 2 oz copper tied to ground except for a few signal traces . the curves demonstrate that the heat from the mosfet can be effectively transferred out of the package through the out pins and only requires a minimum sized sense pad under the package . however for small boards the larger sense area does reduce the junction temperature when sourcing higher currents. downloaded from: http:///
ltc 4233 18 4233f for more information www.linear.com/ltc4233 applications information additional applications the ltc4233 has a wide operating range from 2.9 v to 15 v. the uv , ov and pg thresholds are set with few resistors . all other functions are independent of supply voltage.in addition to hot swap applications , the ltc4233 also functions as a backplane resident switch for removable load cards (see figure 9). figure 10 shows a 3.3 v application with a uv threshold of 2.87v, an ov threshold of 3.77 v and a pg threshold of 3.05v. the last page shows a 20 a parallel application where the two ltc4233 parts each provide 10 a to the load . the pnps prevent one ltc4233 from faulting off in current limit until both parts hit the 11.2 a limit . the pnps are disconnected when power good is false via the series mosfets m1 and m2. figure 9. 12v, 10a backplane resident application with insertion activated turn-on ltc4233 gnd v dd pgov sense C sensetimer intv cc out fb f lt uv r5150k r6 20k r710k r1226k 12v r220k c1 1f v out 12v10a r mon 20k *tvs z1: diodes inc. smaj17a 4233 f09 r420k r3 140k adc 12v load z1* uv = 9.88vov = 15.2v pg = 10.5v i set i mon gate ltc4233 gnd v dd uv f lt ov sense C sensetimer intv cc out fb pg r414.7k r5 10k r23.16k r117.4k r310k c l 680f v out 3.3v10a r mon 20k 4233 f10 r710k adc + c1 1f 3.3v z1* *tvs z1: diodes inc. smaj17a uv = 2.87vov = 3.77v pg = 3.05v i set i mon gate figure 10. 3.3v, 10a card resident application with auto-retry downloaded from: http:///
ltc 4233 19 4233f for more information www.linear.com/ltc4233 information furnished by linear technology corporation is believed to be accurate and reliable . however, no responsibility is assumed for its use . linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights . package description whh package variation: whh38ma 38-lead plastic qfn (5mm 9mm) (reference ltc dwg # 05-08-1934 rev ?) please refer to http:// www .linear.com/designtools/packaging/ for the most recent package drawings. 5.00 0.10 (2 sides) pin 1top mark (see note 6) 12 bottom viewexposed pad 3.59 0.10 3.59 0.05 4.14 0.10 2.93 0.10 4.14 0.05 2.93 0.05 9.00 0.10 (2 sides) 3.59 0.05 5.5 0.05 4.1 0.05 2.7 0.05 3.59 0.10 (whh36ma) qfn 1212 rev ? 7.50 ref 0.40 0.10 0.5 bsc 0.25 0.05 0.50 ref 1.22 ref 0.72 ref 0.203 ref recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 0.350 ref 0.00 C 0.05 seating plane 0.90 0.10 0.70 0.05 0.70 0.05 0.35 ref 0.5 bsc 0.7 bsc 0.9 0.10 7.5 ref (2 sides) 0.25 0.05 package outline pin 1 notchr = 0.30 (reference ltc dwg # 05-08-1934 rev ?) 0.7 bsc 2.7 ref note: 1. drawing is not a jedec package outline 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.5 ref 1.22 ref 0.72 ref downloaded from: http:///
ltc 4233 20 4233f for more information www.linear.com/ltc4233 ? linear technology corporation 2015 lt 0715 ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com/ltc4233 related parts typical application part number description comments ltc4210 single channel hot swap controller operates from 2.7v to 16.5v, active current limiting, sot23-6 ltc4211 single channel hot swap controller operates from 2.5v to 16.5v, multifunction current control, msop-8 or msop-10 ltc4212 single channel hot swap controller operates from 2.5v to 16.5v, power-up timeout, msop-10 ltc4214 negative voltage hot swap controller operates from 0v to C16v, msop-10 ltc4215 hot swap controller with i 2 c compatible monitoring operates from 2.9v to 15v, 8-bit adc monitors current and voltage ltc4217 2a integrated hot swap controller operates from 2.9v to 26.5v, adjustable 5% accurate current limit ltc4218 hot swap controller with 5% accurate 15mv current limit operates from 2.9v to 26.5v, adjustable current limit, ssop-16, dfn-16 ltc4219 5a integrated hot swap controller 12v and 5v preset versions, 10% accurate current limit lt ? 4220 positive and negative voltage, dual channel, hot swap controller operates from 2.7v to 16.5v, ssop-16 ltc4221 dual hot swap controller/sequencer operates from 1v to 13.5v, multifunction current control, ssop-16 ltc4227 dual ideal diode and single hot swap controller operates from 2.9v to 18v, powerpath? and inrush current control for redundant supplies ltc4228 dual ideal diode and hot swap controller operates from 2.9v to 18v, powerpath and inrush current control for two rails, microtca, redundant power supplies, and supply holdup applications ltc4230 triple channel hot swap controller operates from 1.7v to 16.5v, multifunction current control, ssop-20 ltc4232 5a integrated hot swap controller operates from 2.9v to 15v, adjustable 10% accurate current limit ltc4234 20a guaranteed soa hot swap controller operates from 2.9v to 15v, adjustable 11% accurate current limit 12v, 20a parallel application ltc4233 0.1f 12v v out 12v20a timer out gnd pg i set i mon gate fb *tvs z1: diodes inc. smaj17a uv f lt ov sense C sense intv cc 107k5.23k 10k 150k20k 150k 20k 1000f 100k 1f 107k5.23k 10k 1f m2vn2222llg q2 2n5087 q12n5087 m1 vn2222llg ltc4233 0.1f timer out v dd v dd pg i set i mon gate fb 4233 ta02 z1* gnd uv f lt ov sense C sense intv cc + downloaded from: http:///

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